图像等数据的采集与标注。
软件、系统、硬件相关测试辅助。
计算机相关专业,大专及以上院校在读学生
1. 云端服务API后台开发
2. 云端数据管理平台的开发
1. 学习能力强,对新技术保持好奇心
2. 优秀的数据结构、基本算法、网络、并发编程等基础知识
3. 对服务器端程序性能优化有经验
4. 较好的动手解决问题的能力,对开源的工具有广泛的了解
5. python/php/java/nodejs/c 等主流的语言,熟练使用一种
6. 本科及以上学历,三年以上后台开发经验
7. 有物联网产品后台开发或者机器学习经验者优先
1. 智能人机交互(图像处理、计算机视觉检测跟踪识别、输入信号处理、语音合成、语音识别)产品开发工作
2. 图像/语音相关SDK的开发
3. 图像/语音数据的收集和处理平台搭建与开发
1. 熟练掌握Java/C++/C语言开发和设计模式
2. 熟悉驱动开发
3. 有Android应用(含NDK)开发经验,熟悉Linux环境编程
4. 有iOS应用开发经验
5. 有计算机视觉图像处理、物体检测跟踪识别、语音输入信号处理、语音识别、语音合成或自然语言处理相关研发经验者优先考虑
6. 有图像/语音数据分析,挖掘,和数据仓库建模的项目实践经验者优先
7. 工作认真负责,严谨细致,对技术富有钻研精神,有良好的创新精神和团队精神
1. 负责研究SLAM、多传感器融合、地图构建以及定位等算法
2. 负责算法在嵌入式平台的实现、优化以及产品化
3. 负责算法计算性能优化,并推动其应用
1. 计算机及相关专业,硕士及以上学历
2. 理解成像原理,具有投影几何的基本知识
3. 熟悉基本图像处理算法,有opencv的使用经验
4. 精通C++ (包含C++11.0)
5. 线性代数基础扎实
6. Matlab技能是一个strong plus
7. 熟悉Linux环境是一个strong plus
8. 较强的逻辑思维能力以及算法实现能力
9. 具有良好的沟通能力和团队合作精神
1. 负责需求调研、可行性分析和方案设计
2. 负责嵌入式系统驱动开发与调试,系统移植与优化以及核心应用代码编写和调试
3. 负责硬件生产与测试相关工具的开发
4. 负责提升产品的质量、性能和稳定性
1. 本科学历,计算机相关专业
2. 5年或以上嵌入式软件开发经验,熟悉软件开发流程
3. 精通C/C++语言,具有良好的代码编写习惯
4. 精通Linux操作系统环境编程
5. 熟悉ARM处理器架构与基本硬件接口
6. 具有CUDA编程经验开发者优先
7. 具有Camera嵌入式软件开发经验者优先
8. 具有深度学习相关算法在终端开发与优化经验者优先
9. 具有较强逻辑分析能力、学习能力和独立解决问题的能力
10. 具有良好的沟通能力和团队合作精神,具有强烈的责任心和钻研精神
1. 负责计算机视觉、深度学习相关的技术系统与产品的研发工作
2. 负责计算机视觉、深度学习相关方向的技术难点攻关与前瞻研究
3. 负责算法计算性能优化,并推动其上线应用
1. 创造性思维,富有想象力,有推进人工智能的理想和使命感
2. 在深度学习、统计机器学习、计算机视觉、最优化方法等方面有较深入的研究
3. 熟悉物体(人体、人脸、通用目标)检测、跟踪与识别的基本算法
4. 较强的逻辑思维能力以及算法实现能力
5. 具有良好的沟通能力和团队合作精神
1. 负责机器学习算法的研究和开发
2. 负责常用机器学习框架(caffe,theano,torch)的搭建
3. 负责图像识别库training dataset采集,整理,训练
1. 计算机专业、机器学习专业、自然语言处理,生物工程,人工智能,统计学相关专业
2. 硕士学历三年(含)以上机器学习/模式识别开发经验,博士一年(含)以上机器学习/模式识别经验
3. 精通Matlab/Python/C++等编程语言,熟悉嵌入式系统开发
4. 能够熟练阅读英文技术资料并撰写英文技术文档
5. 具有工作主动自觉性和较快的适应工作能力,具有团队精神、较强的分析和表达能力
1. Creating test plan according to design spec
2. Designing and developing verification environment;
3. Debugging SoC regression failure
4. Creating system checker/monitors and system UVCs, code & function coverage in SOC
5. Creating C test case running on ARM in SOC
6. Creating UVM test case in SOC
1. Education and Experience-Bachelor or above with 3 years of work experience
2. Skills and Knowledge-
Verilog
System Verilo
UVM
Perl/Python/Tcl
AXI/AHB/APB
Co-sim between hardware and software is an additional plus
C/C++ is an additional plus
MIPI/USB/Ethernet/PCIE/SATA/SPI/I2C/etc. experience is an additional plus
ARM related experience is an additional plus
1. Participate in SoC level DFT architecture definition.
2. Implement DFT strategy for the SoC chips, cooperating with design team
3. Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
4. Develop the high coverage and cost effective test patterns.
5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.
6. Support other teams for DFT related problems.
1. Either Bachelor or Master degree, 2+ years related experience required.
2. Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA
3. Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG.
4. Knowledge on and familiar with basic Mentor/ Synopsys DFT flow and tools
5. Proficient in Verilog/VHDL language
6. Be familiar with Shell/TCL/Perl program, or skilled in C program
7. Good English communication skills
8. Self-motivated and good team player
1. Understanding algorithm requirement and implement with verilog
2. System verification, debugging and performance analyzing
3. Building block level verification environment, writing block level test vectors.
4. Prepare architecture specification for IC circuits and assist in ensuring correct circuit implementation.
5. RTL coding to verify against circuit implementation; Perform integration into SOCs.
6. Verify functions by creating test cases, and modify test benches to work with internal simulation environment.
7. Develop test environments and analysis coverage.
8. Module and chip level synthesize with sdc/upf.
9. Assist with chip bring up and perform silicon functional/performance validation.
10. Define timing and power specifications, and identify timing solutions.
11. Assist with backend team on perform place-and-route and timing analysis of modules
1. BS or above in EE or related
2. 5+ years of working experiences in ASIC design
3. Strong Verilog programming ability, familiar with mainstream of frond-end ASIC design flow & design tools
4. Perl, Shell and C++ scripting language is a must
5. Familiar with frontend integration flow
6. Strong problem solving and debugging skills
7. Knowledge of image processing is a plus
8. Good communication skills and strong team-player mindset